The present invention relates to a method of manufacturing a semiconductor device and can be used appropriately as a method of manufacturing, e.g., a semiconductor device having a nonvolatile memory.
As an electrically writable/erasable nonvolatile semiconductor storage device, an EEPROM (Electrically Erasable and Programmable Read Only Memory) has been used widely. Such a storage device represented by a flash memory which is currently used widely has a conductive floating gate electrode or a trapping insulating film surrounded by oxide films under the gate electrode of a MISFET. A charge storage state in the floating gate electrode or trapping insulating film is used as stored information and read as the threshold of the transistor. The trapping insulating refers to an insulating film capable of storing charges therein, and examples thereof include a silicon nitride film. By injection/release of charges into/from such a charge storage region, the threshold of the MISFET is shifted to allow the MISFET to operate as a storage element. Examples of the flash memory include a split-gate cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film. In such a memory, a silicon nitride film is used as a charge storage region. This provides advantages over a conductive floating gate film such that, due to discrete storage of charges, data retention reliability is high, and the high data retention reliability allows the oxide films over and under the silicon nitride film to be thinned and allows a voltage for a write/erase operation to be reduced.
Each of Japanese Unexamined Patent Publications Nos. 2007-281092 (Patent Document 1) and 2011-49282 (Patent Document 2) describes a technique related to a nonvolatile semiconductor storage device. On the other hand, each of Japanese Unexamined Patent Publications Nos. 2006-049781 (Patent Document 3) and Hei 11(1999)-126900 (Patent Document 4) and Japanese Translation of PCT Application No. 2009-500823 (Patent Document 5) describes a technique for forming sidewall spacers over the side walls of a gate electrode.